Within CMOS technologies, there is a need to create Field-Effect Transistors (FETs) with multiple gate dielectrics within a chip. By way of example, multiple gate dielectric thicknesses are required for different device performance and product requirements. Thin dielectrics are often required for high performance logic, whereas, thicker dielectrics are required to support I/O circuitry that operates at higher voltages. It is also desirable to create areas within a semiconductor chip containing distinct gate dielectric composition. The different gate dielectric compositions can include oxides, nitrides, oxynitrides, high-K dielectrics, or stacked combinations of these films. These dielectrics possess different properties, including leakage, capacitance, mobility, interface quality, reliability, charge trapping, and diffusion barrier characteristics. By placing different dielectrics in areas of the circuit that can benefit from the specific properties of that dielectric, the overall performance of the semiconductor chip can be optimized.
Beyond the previously mentioned FET application of multiple gate dielectric formation, additional thickness or composition gate dielectrics may be required for capacitor applications such as decoupling capacitors or DRAM storage capacitors, to optimize the requirements for gate leakage and capacitance per unit area.
However, there are limitations with current integration schemes. For example, a standard integration sequence is to grow the thicker (first) dielectric over the entire wafer, then using a lithographic mask, wet etching areas in which the thin (second) dielectric is to be grown. In this integration scheme, the substrate surface within areas where the thin (second) dielectric is to be formed is always subjected to a resist strip process which grows a chemical oxide. This chemical oxide is incorporated into the thinner second oxide and can compromise the dielectric quality. Using this type of integration sequence also results in exposing the thin (second) dielectric area to an additional wet etch process, which can degrade the interface quality by inducing surface roughening. These degradation mechanisms in the thin dielectric area are particularly problematic because the thinner dielectric is generally the critical area of the semiconductor chip that requires the highest quality. Similar disadvantages exist with standard integration schemes that create multiple dielectric composition areas within a chip.
Accordingly, there exists a need in the art to overcome the deficiencies and limitations described hereinabove.